The complexity and sophistication of present-day integrated circuit (IC) chips have advanced significantly over those of early chip designs. Where formerly a chip might embody relatively simple electronic logic blocks affected by interconnections between logic gates, currently chips can include combinations of complex, modularized IC designs often called “cores” which together constitute an entire SOC.
In general, IC chip development includes a design phase and a verification phase for determining whether a design works as expected. The verification phase has moved increasingly toward a software simulation approach to avoid the costs of first implementing designs in hardware to verify them
A key factor for developers and marketers of IC chips in being competitive in business is time-to-market of new products, the shorter the time-to-market, the better the prospects for sales. Time-to-market in turn depends to a significant extent on the duration of the verification phase for new products to be released. As chip designs have become more complex, shortcomings in existing chip verification methodologies, which extend time-to-market have become evident.
Typically, in verifying a design, a simulator is used. Here, “simulator” refers to specialized software whose functions include accepting software written in a hardware description language (HDL) such as Verilog or VHDL which models a circuit design (for example, a core as described above), and using the model to simulate the response of the design to stimuli which are applied by a test case to determine whether the design functions as expected. The results are observed and used to de-bug the design.
In order to achieve acceptably bug-free designs, verification software must be developed for applying a number of test cases sufficient to fully exercise the design in simulation. In the case of SOC designs, the functioning of both the individual cores as they are developed, and of the cores functioning concurrently when interconnected, as a system must be verified. Moreover, a complete SOC design usually includes an embedded processor core and an I/O controller. Simulation, which includes a processor core, tends to require an inordinate amount of time and computing resources, largely because the processor is usually the most complex piece of circuitry on the chip and interacts with many other cores. Simulation, which includes an I/O controller, tends to require an inordinate amount of new software or software modification because the specific I/O cores, pin connections, number of pins, etc. vary from design to design.
It can be appreciated from the foregoing that verification of an SOC can severely impact time-to-market, due to the necessity of developing and executing software for performing the numerous test cases required to fully exercise the design.
However, inefficiencies in current verification methodologies exacerbate time pressures. For example, design specific verification software must be written or the existing software modified for each specific chip design to be verified. With today=s exceedingly complex SOC designs, even modification of existing software is expensive and time consuming. One particularly time-consuming need is to write or modify the software needed for verifying I/O pin muxing of SOC cores to I/O pin driver models. Simulation of pin muxing presents unique challenges because some I/O pin driver models cannot be turned off and there is no standard established for turning on/off those models that can be turned on/off.
A design verification system is needed which will reduce the amount of chip specific design verification software required, especially for verification of pin-muxing, as well as reduce the time to collect and integrate that software.